The present technique relates to mechanisms for generating and processing a trace stream indicative of activities of processing circuitry within a data processing system, and in particular to mechanisms for efficiently generating a data trace stream in situations where the sequence of instructions executed by the processing circuitry includes at least one predicated vector memory access instruction.
Trace circuitry can be used to produce one or more trace streams comprising a series of trace elements, such that those trace elements can later be analysed in order to determine activities of associated processing circuitry. For example, an instruction trace stream can be generated that includes a number of trace elements enabling analysis circuitry to later determine the sequence of instructions executed by the processing circuitry. Further, if desired, a data trace stream can be produced that also comprises a plurality of trace elements to enable analysis circuitry to later determine information about memory addresses (and optionally data values) accessed when the processing circuitry executed memory access instructions within the sequence of instructions.
Some data processing systems support processing of vector instructions, and within such vector processing systems, vector memory access instructions can be executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. Further, in modern systems it is possible to apply predication to such instructions, so that certain lanes are omitted from the operation.
It would be desirable to provide an efficient tracing mechanism to be used by trace circuitry when producing a data trace stream in association with predicated vector memory access instructions.